Fast optimization of CMOS circuits is needed to reduce design cycle time and chip cost and to enhance yield. Mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have largely automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills and design cycle time. In this paper, two novel design flows are presented for fast multiobjective optimization of nano-CMOS circuits: actual-value optimization and normalized-value optimization. The design flows consider two characteristics for optimization i.e. power and frequency in a current-starved 50 nm voltage-controlled oscillator (VCO). Accurate polynomial-regression based models have been developed for power (including leakage) and frequency of the VCO to speedup the design optimization. In the actual-value optimization flow, the power model is minimized using genetic algorithm, while treating frequency View the MathML source as a constraint. The actual-value optimization flow achieved 21.67% power savings, while maintaining a frequency View the MathML source. In the normalized-value optimization flow, the normalized form of these models are subjected to a weighted optimization using genetic algorithm. The normalized-value optimization flow achieved 16.67% power savings, with frequency View the MathML source. It is observed that while the actual-value optimization approach provides a better exploration of the design space, the normalized-value optimization approach provides a ≈5× speedup in the computation time.