Therehas always been anincreasing interest in the development of new arithmetic processors. The objective of this paper is to describe the hardware implementation of a pipelined arithmetic processorpublished previously, which can add, subtract,multiply,divide,square and square root the binary numbers. The processor described resulted in 46input/output pins.The MOSIS and cadence fabrication technology generally allow up to 40 pins. In this paper hardware implementation of arithmetic processor is taken up so that processor chip can be developed by 40 pins. This hardware implementation will lead to better implementation of handling input, output pins for future processors. The hardware implementation of the modified array has been done using Simulink and tested. It is hoped that this research will lead to the design and VLSI implementation of new arithmetic proce